Adders are well known in the data processing art as circuits which perform mathematical addition. Typically, such adders perform this addition operation by using binary inputs to generate binary outputs using "carry" information with a full adder circuit implementation or by not using "carry" information with a half adder circuit implementation.
It is possible to build multi-bit adder circuits using much the same form as the full and half adder circuits known in the data processing art. For multi-bit adders, a common implementation combines the binary inputs to form "carry generate" (C.sub.g), "carry propagate" (C.sub.p) and "carry kill (also referred to as "carry zero") (C.sub.k or C.sub.z) signals, which ease generation of the "carry out" signal. A general set of equations for representing these signals are: EQU C.sub.g (i)=A(i) AND B(i); EQU C.sub.p (i)=A(i) XOR B(i); EQU C.sub.k (i)=A(i) OR B(i).
Forming the full-adder Sum bit using the C.sub.g, C.sub.p, and C.sub.k signals can be represented as: EQU Sum(i)={Carry.sub.-- in(i) AND [C.sub.k (i) OR C.sub.g (i)]} OR C.sub.p (i) .
To generate the carry-in(i) signal, a recursive equation is used of the form: EQU Carry.sub.-- in(i-1)=C.sub.g (i-1) OR C.sub.p (i-1) AND [C.sub.g (i-2) OR C.sub.p (i-2) AND { }],
where the "C.sub.g () OR C.sub.p () AND" becomes a recursion, back to the Carry.sub.-- in signal, and would be placed in the "{ }" above. There exist many different circuits to implement the "Carry.sub.-- in(i)" term for each successive full-adder.
It should be noted that the adders described above, as well as other types of adders implemented in prior art systems, generally provide a binary output. For information on BCD and binary adders, refer to U.S. Pat. No. 5,007,010 by Laurence P. Flora, issued Apr. 9, 1991 and U.S. Pat. No. 5,450,340 by Michael Nicolaidis, issued Sep. 12, 1995. With binary true/complement outputs, one bit will be driven to a logic high level during operation of the adder. This requirement will result in excessive power consumption in some data processing applications as multiple lines must be driven to a logic high level many times during operation thereof.
As power consumption becomes increasingly important in today's portable data processing applications, the power consumed by a commonly used element, such as an adder, in a data processing system, becomes increasingly relevant. Thus, it is desirable to decrease the power consumption of an adder circuit in such data processing systems.